CISC VS RISC computers (all details)

Recommendation System literature review | Building a recommendation system

People have always relied on the recommendations from their peers or the advice of experts to support their decision making. Amazon.com has been using collaborative filtering for a decade to recommend products to their customers, and Netflix valued improvements to the recommender technology underlying their movie rental service at $1M via the widely published Netflix Prize [6]. Research on recommender algorithms garnered significant attention in 2006 when Netflix launched the Netflix Prize to improve the state of movie recommendation. The objective of this competition was to build a recommender algorithm that could beat their internal CineMatch algorithm in offline tests by 10%. It sparked a flurry of activity, both in academia and amongst hobbyists. The $1 M prize demonstrates the value that vendors place on accurate recommendations [8]. Recommender Systems provide the users with the suggestions of information that may be useful to the users to make their decisions on various sit

CISC VS RISC computers (all details)

CISC

Introduction

The term "CISC" (complex instruction set computer or computing) refers to computers designed with a full set of computer instructions that were intended to provide needed capabilities in the most efficient way.

Intel's Pentium microprocessors are CISC microprocessors. CISC is a processor design where single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) or are capable of multi-step operations or addressing modes within single instructions.

The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. This is achieved by building processor hardware that is capable of understanding & executing a series of operations, this is where our CISC architecture introduced.

The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. Computers based on the CISC architecture are designed to decrease the memory cost. Because, the large programs need more storage, thus increasing the memory cost and large memory becomes more expensive. To solve these problems, the number of instructions per program can be reduced by embedding the number of operations in a single instruction, thereby making the instructions more complex. CISC uses minimum possible instructions by implementing hardware and executes operations.

Examples of CISC PROCESSORS

IBM 370/168 – It was introduced in the year 1970. CISC design is a 32 bit processor and four 64-bit floating point registers.

VAX 11/780 – CISC design is a 32-bit processor and it supports many numbers of addressing modes and machine instructions which is from Digital Equipment Corporation.

Intel 80486 – It was launched in the year 1989 and it is a CISC processor, which has instructions varying lengths from 1 to 11 and it will have 235 instructions.

History of CISC

— The first PC microprocessors developed were CISC chips, because all the instructions the processor could execute were built into the chip. Memory was expensive in the early days of PCs, and CISC chips saved memory because their programming could be fed directly into the processor. CISC was developed to make compiler development simpler. It shifts most of the burden of generating machine instructions to the processor. For example, instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor would have a built-in ability to do this.

Features of CISC

1. CISC are easy to program and which makes efficient use of memory .Since the earliest machines were programmed in assembly language and memory was slow and expensive ,the CISC philosophy made sense, and was commonly implemented in such large computers as the PDP-11 and the DEC system .

2. Most common microprocessor designs such as the Intel 80x86 and Motorola 68K series followed the CISC philosophy.

3. CISC was developed to make compiler development simpler. It shifts most of the burden of generating machines instructions to the processor. For example , instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor would have a built-in ability to do this.

4. A large number of instructions are used in CISC microprocessors—typically from 100 to 250 instructions.

5. A large variety of addressing modes—typically from 5 to 20 different modes.

Advantages of CISC

1. Microprogramming is as easy as assembly language to implement and much less expensive than hardwiring a control unit.

2. Directly supported high-level programming constructs combined into single instructions.

3. The compact nature of such instruction sets resulted in smaller program sizes and fewer calls to main memory which meant good programming productivity.

4. Many designs achieved the aim of higher throughput at lower cost and also allowed high-level language constructs to be expressed by fewer instructions.

5. CISC was developed to make compiler development simpler.

Disadvantages of CISC

1. Earlier generations of a processor family generally were contained as a subset in every new version - so instruction set & chip hardware become more complex with each generation of computers.

2. Many specialized instructions aren't used frequently enough to justify their existence -approximately 20% of the available instructions are used in a typical program.

3. The invention of Pipelining made CISC less efficient because the CISC instruction could not be broken up into smaller parts that could be run simultaneously.

4. When memory became less expensive, it became less important to create instruction sets that called main memory fewer times

RISC

Introduction:

RISC (Reduced Instruction Set Computer) is used in portable devices due to its power efficiency. For Example, Apple iPod and Nintendo DS. RISC is a type of microprocessor architecture that uses highly-optimized set of instructions. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program Pipelining is one of the unique feature of RISC. It is performed by overlapping the execution of several instructions in a pipeline fashion. It has a high performance advantage over CISC.

History of RISC

JOHN COCKE was known as the “father of RISC architecture”

In 1974– John Cocke (IBM) proved that 80% of work was done using only 20%of the instruction .This sparked 3 RISC based research projects

1. IBM 801 machine in 1974

2. Berkeley’s RISC-I and RISC-II processors in 1980

3. And Stanford’s MIPS processor in 1981

The first investigations into computer architectures that later became known as RISC processors did not originate in the microprocessor industry. John Cocke at IBM is usually given credit for the concept of the RISC computer. In 1974 IBM was involved in a project to design a complex telephone-switching network that required a real-time response and a very fast processor (for the time). Although the project was terminated in 1975, the design work at IBM had highlighted some of the issues at the heart of high-speed computer design. It was clear that a fast computer should avoid direct arithmetic operations on memory (i.e., no instructions such as ADD R0,memory), have a uniform instruction format , include instruction pipelining (i.e., starting executing a new instruction before the current instruction has been completed), and take account of the problems caused by branch instructions.

1975If the RISC philosophy is so appealing, why was it not developed much earlier? The short answer to this question is that RISC architectures make sense only in a 32-bit world, because RISC processors rely on long instruction formats to help overcome the effect of the processor-memory bottleneck. In other words, it is the progression from 8-bit and 16-bit architectures to 32-bit architectures that has made the development of RISC architectures almost inevitable.

RISC ARCHITECTURE CHARACTERISTICS

Simple Instructions are used in RISC architecture.

RISC helps and supports few simple data types and synthesize complex data types.

RISC utilizes simple addressing modes and fixed length instructions for pipelining.

RISC permits any register to use in any context.

One Cycle Execution Time

The amount of work that a computer can perform is reduced by separating “LOAD” and “STORE” instructions.

RISC contains Large Number of Registers in order to prevent various number of interactions with memory.

In RISC, Pipelining is easy as the execution of all instructions will be done in a uniform interval of time i.e. one click.

In RISC, more RAM is required to store assembly level instructions.

Reduced instructions need a less number of transistors in RISC.

RISC uses Harvard memory model means it is Harvard Architecture.

A compiler is used to perform the conversion operation means to convert a high-level language statement into the code of its form.

Pipelining: A key RISC technique

Pipelining is a design technique where the computer’s hardware processes more than one instruction at a time and does not wait for one instruction to complete before starting the next.

The performance of a pipelined system depends on the time it takes only for any one stage to be complicated-not on the total time for all stages as with non-pipelined designs. In a typical pipelined RISC design, each instruction takes one clock cycle for each stage, so the processor can accept one new instruction per clock. Pipelined does not improve the latency of instructions (each instruction still requires the same amount of time to complete), but it does improve the overall throughout.

Advantages:-

Compiler has to do very little work to translate a high-level language statement into assembly
Length of the code is relatively short
Very little RAM is required to store instructions
The emphasis is put on building complex instructions directly into the hardware.

5. RISC has fixed instruction set which helps decoding process easy.

RISC has large number of registers and hence less dependency on memory location
RISC has small instruction set
More than 95% of instructions are executed with only one clock cycle, and many of 5% instructions are executed with 2 clock cycles which is not the case with CISC
RISC has separate buses for data and code(referred to as Harvard architecture).
One of most important point is that RISC uses load/store architecture.

Disadvantages of RISC

1. With the increase in length of the instructions, the complexity increases for the RISC processors to execute due to its character cycle per instruction.

2. The performance of the RISC processors depends mostly on the compiler or programmer as the knowledge of the compiler plays a major role while converting the CISC code to a RISC code; hence, the quality of the generated code depends on the compiler.

3. While rescheduling the CISC code to a RISC code, termed as a code expansion, will increase the size. And, the quality of this code expansion will again depend on the compiler, and also on the machine’s instruction set.

4. The first level cache of the RISC processors is also a disadvantage of the RISC, in which these processors have large memory caches on the chip itself. For feeding the instructions, they require very fast memory systems.